1. Field of the Invention
The present invention relates to an improvement in or relating to a bus which is used in connecting CPUs, memories and other components in computer systems.
2. Description of the Prior Art
As seen from FIG. 11, CPUs, memories and other components are fixed to substrate plates 1 with male or female elements of connectors 2, thus constituting component panels. These component panels are spaced and arranged parallel to each other with their connector elements 2 facing and connected to data, control, address and other buses 3.
Arrangement of component panels along an extended length of bus will inevitably cause transmission time of data between selected component panels to substantially vary depending on whether these component panels are selected within a relatively shorter range or within a relatively longer range.
This arrangement, therefore, requires the controlling of transmission time to reduce uneven delay of data transmission time due to different travelling distances between selected component panels. This makes the controlling of data transmission complicated, and makes quick transmission and processing of data difficult.